The present invention relates to the fabrication of semiconductor integrated circuits (ICs). More particularly, the present invention relates to methods for inspecting under-etched vias.
In semiconductor IC fabrication, devices such as component transistors are formed on a semiconductor wafer or substrate, which is typically made of silicon. Successive layers of various materials may be deposited onto the wafer or substrate to form a layer stack. Very large scale integration (VLSI) chips often require more than a single level of metal to provide sufficient interconnection capability. Semiconductor IC fabrication processes typically use vias to interconnect multi-layer metal levels. During the fabrication process, the vias are usually etched or drilled through the dielectric or insulator layer.
Unfortunately however, etching or forming vias through the dielectric or insulator layer often does not result in completely etched vias. As an example, Prior Art FIG. 1 illustrates a cross section of a silicon wafer stack 100 having a plurality of vias 110, 112, 114, 116, 118, and 120. Wafer stack 100 comprises a wafer 102, an oxide layer 104, a metal layer 106, and a dielectric layer 108 having vias 110 through 120. As shown in FIG. 1, vias 110, 114, 116, and 120 do not come in direct contact with metal layer 106. Vias 110, 114, 116, and 120 are commonly referred to as "under-etched" vias since they have not been etched completely through dielectric layer 108. These under-etched vias may cause an open circuit by preventing electrical contact between an upper metal layer which may be subsequently deposited above dielectric layer 108 and lower metal layer 106. On the other hand, vias 112 and 118 are properly etched because they have been etched completely through dielectric layer 108. Since vias 112 and 118 come in direct contact with metal layer 106, no open circuit results between an upper metal layer and lower metal layer 106. Those skilled in the art will appreciate that layers 104, 106, and 108 can be disposed on wafer 102 in a different order and that the vias can be formed on any one of layers 104, 106, and 108.
It should also be noted that the silicon wafer layer stack 100 of Prior Art FIG. 1 is shown for illustration purposes only and other additional layers, which have not been described, may be present above, below, and between the layers shown. These other layers may be used to provide, for example, additional interconnecting layers or layers from which components may be formed. Further, not all of the shown layers need necessarily be present and some or all may be substituted by other different layers.
In the past, detecting the under-etched vias has presented problems due to the size and number of vias in a wafer, which can number into millions in a single chip using sub-micron technology. Several conventional methods have been devised to detect under-etched vias in a wafer stack. One method uses a scanning electron microscope (SEM) to look at a cross section of a wafer. Specifically, the wafer is broken at the cross section. The SEM is then used to look at the vias along the cut cross section of the wafer. However, the SEM method has several drawbacks. First, the SEM equipment is typically very expensive. Second, cutting the wafer through the cross section requires non-trivial preparation, which is time consuming. Finally, the observable vias through the cut cross section is small compared to the number of vias on the entire wafer, which may run into millions.
Another prior art method utilizes a profilometer to check for the under-etched vias. The profilometer is basically a needle which follows the contour of a wafer. Unfortunately, the profilometer cannot be used on a regular wafer featuring, for example, the 0.25 or sub -0.25 micron technology. Instead, a much larger test structure must be created to use the profilometer. This larger test structure does not accurately reflect the features of the regular wafer sample. For example, the etch rates can differ significantly between the regular wafer sample and the larger test structure.
In addition, a traditional method used an equipment called "atomic force microscope" (AFM) to check for the under-etched vias. Specifically, the AFM probed a needle into the vias to check whether the needle sensed a metal or a dielectric. The method using AFM has several drawbacks. First, the AFM equipment is very expensive. Second, it can detect only a limited number of vias. Finally, the AFM equipment is difficult to operate because the mechanical needle must actually be inserted into a via.
In view of the foregoing, what is desired is improved methods for detecting under-etched vias in a wafer stack.